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19-2835; Rev 0; 4/03
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC
General Description
The MAX1192 is an ultra-low-power, dual, 8-bit, 22Msps analog-to-digital converter (ADC). The device features two fully differential wideband track-and-hold (T/H) inputs. These inputs have a 440MHz bandwidth and accept fully differential or single-ended signals. The MAX1192 delivers a typical signal-to-noise and distortion (SINAD) of 48.6dB at an input frequency of 5.5MHz and a sampling rate of 22Msps while consuming only 27.3mW. This ADC operates from a 2.7V to 3.6V analog power supply. A separate 1.8V to 3.6V supply powers the digital output driver. In addition to ultra-low operating power, the MAX1192 features three power-down modes to conserve power during idle periods. Excellent dynamic performance, ultra-low power, and small size make the MAX1192 ideal for applications in imaging, instrumentation, and digital communications. An internal 1.024V precision bandgap reference sets the full-scale range of the ADC to 0.512V. A flexible reference structure allows the MAX1192 to use its internal reference or accept an externally applied reference for applications requiring increased accuracy. The MAX1192 features parallel, multiplexed, CMOScompatible tri-state outputs. The digital output format is offset binary. A separate digital power input accepts a voltage from 1.8V to 3.6V for flexible interfacing to different logic levels. The MAX1192 is available in a 5mm x 5mm, 28-pin thin QFN package, and is specified for the extended industrial (-40C to +85C) temperature range. For higher sampling frequency applications, refer to the MAX1195-MAX1198 dual 8-bit ADCs. Pin-compatible versions of the MAX1192 are also available. Refer to the MAX1191 data sheet for 7.5Msps, and the MAX1193 data sheet for 45Msps.
Features
o Ultra-Low Power 27.3mW (Normal Operation: 22Msps) 1.8W (Shutdown Mode) o Excellent Dynamic Performance 48.6dB/47.2dB SNR at fIN = 5.5MHz/125MHz 70dBc/69dBc SFDR at fIN = 5.5MHz/125MHz o 2.7V to 3.6V Single Analog Supply o 1.8V to 3.6V TTL/CMOS-Compatible Digital Outputs o Fully Differential or Single-Ended Analog Inputs o Internal/External Reference Option o Multiplexed CMOS-Compatible Tri-State Outputs o 28-Pin Thin QFN Package o Evaluation Kit Available (Order MAX1193EVKIT)
MAX1192
Ordering Information
PART MAX1192ETI-T TEMP RANGE -40C to +85C PIN-PACKAGE 28 Thin QFN-EP* (5mm x 5mm)
*EP = Exposed paddle.
Pin Configuration
TOP VIEW
REFIN REFN REFP COM PD0 PD1 VDD
28
27
26
25
24
23
Applications
Ultrasound and Medical Imaging IQ Baseband Sampling Battery-Powered Portable Instruments Low-Power Video WLAN, Mobile DSL, WLL Receiver
22
INAINA+ GND CLK GND INB+ INB-
1 2 3 4 5 6 7
EXPOSED PADDLE
21 20 19
D0 D1 D2 D3 A/B D4 D5
MAX1192
18 17 16 15 12 13
D7
10
11
GND
OGND
5mm x 5mm THIN QFN ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
OVDD
VDD
VDD
D6
14
8
9
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC MAX1192
ABSOLUTE MAXIMUM RATINGS
VDD, OVDD to GND ...............................................-0.3V to +3.6V OGND to GND.......................................................-0.3V to +0.3V INA+, INA-, INB+, INB- to GND .................-0.3V to (VDD + 0.3V) CLK, REFIN, REFP, REFN, COM to GND ...-0.3V to (VDD + 0.3V) PD0, PD1 to OGND .................................-0.3V to (OVDD + 0.3V) Digital Outputs to OGND .........................-0.3V to (OVDD + 0.3V) Continuous Power Dissipation (TA = +70C) 28-Pin Thin QFN (derated 20.8mW/C above +70C) ..1667mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range ............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL 10pF at digital outputs, fCLK = 22MHz, CREFP = CREFN = CCOM = 0.33F, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error DC Gain Matching Gain Temperature Coefficient Power-Supply Rejection ANALOG INPUT Differential Input Voltage Range Common-Mode Input Voltage Range Input Resistance Input Capacitance CONVERSION RATE Clock Frequency Range Data Latency fCLK Channel A Channel B fIN = 1.875MHz SNR fIN = 5.5MHz fIN = 11MHz Signal-to-Noise and Distortion (Note 2) fIN = 1.875MHz SINAD fIN = 5.5MHz fIN = 11MHz 47 47 7.5 5.0 5.5 48.6 48.6 48.6 48.7 48.6 48.6 dB dB 22 MHz Clock cycles VDIFF VCOM RIN CIN Switched capacitor load Differential or single-ended inputs 0.512 VDD / 2 245 5 V V k pF Offset (VDD 5%) Gain (VDD 5%) INL DNL No missing codes over temperature +25C < +25C Excludes REFP - REFN error 0.01 30 0.02 0.05 8 0.15 0.14 1.00 1.00 4 6 2 0.2 Bits LSB LSB %FS %FS dB ppm/C LSB SYMBOL CONDITIONS MIN TYP MAX UNITS
DYNAMIC CHARACTERISTICS (differential inputs, 4096-point FFT) Signal-to-Noise Ratio (Note 2)
2
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Ultra-Low-Power, 22Msps, Dual 8-Bit ADC
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL 10pF at digital outputs, fCLK = 22MHz, CREFP = CREFN = CCOM = 0.33F, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER Spurious-Free Dynamic Range (Note 2) SYMBOL SFDR fIN = 5.5MHz fIN = 11MHz Third-Harmonic Distortion (Note 2) Intermodulation Distortion Third-Order Intermodulation Total Harmonic Distortion (Note 2) Small-Signal Bandwidth Full-Power Bandwidth Aperture Delay Aperture Jitter Overdrive Recovery Time REFP Output Voltage REFN Output Voltage COM Output Voltage Differential Reference Output Differential Reference Output Temperature Coefficient Maximum REFP/REFN/COM Source Current Maximum REFP/REFN/COM Sink Current VCOM VREF VREFTC ISOURCE ISINK VREFP - VREFN fIN = 1.875MHz HD3 fIN = 5.5MHz fIN = 11MHz IMD IM3 fIN1 = 1MHz at -7dB FS, fIN2 = 1.01MHz at -7dB FS fIN1 = 1MHz at -7dB FS, fIN2 = 1.01MHz at -7dB FS fIN = 1.875MHz THD SSBW FPBW tAD tAJ 1.5 x full-scale input VREFP - VCOM VREFN - VCOM VDD / 2 - 0.15 fIN = 5.5MHz fIN = 11MHz Input at -20dB FS Input at -0.5dB FS CONDITIONS fIN = 1.875MHz 59.0 MIN TYP 70.8 70.0 70.4 75.8 -74.0 -74.8 -64 -67 -71.0 -70.0 -70.2 440 440 1.5 2 2 0.256 -0.256 VDD / 2 0.512 30 2 2 VDD / 2 + 0.15 MHz MHz ns psRMS ns V V V V ppm/C mA mA -57.0 dBc dBc dBc dBc dBc MAX UNITS
MAX1192
INTERNAL REFERENCE (REFIN = VDD; VREFP, VREFN, and VCOM are generated internally)
BUFFERED EXTERNAL REFERENCE (VREFIN = 1.024V, VREFP, VREFN, and VCOM are generated internally) REFIN Input Voltage COM Output Voltage Differential Reference Output Maximum REFP/REFN/COM Source Current VREFIN VCOM VREF ISOURCE VREFP - VREFN VDD / 2 - 0.15 1.024 VDD / 2 0.512 2 VDD / 2 + 0.15 V V V mA
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3
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC MAX1192
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL 10pF at digital outputs, fCLK = 22MHz, CREFP = CREFN = CCOM = 0.33F, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER Maximum REFP/REFN/COM Sink Current REFIN Input Resistance REFIN Input Current REFP Input Voltage REFN Input Voltage COM Input Voltage Differential Reference Input Voltage REFP Input Resistance REFN Input Resistance DIGITAL INPUTS (CLK, PD0, PD1) CLK Input High Threshold VIH PD0, PD1 CLK Input Low Threshold VIL PD0, PD1 Input Hysteresis Digital Input Leakage Current Digital Input Capacitance DIGITAL OUTPUTS (D7-D0, A/B) Output Voltage Low Output Voltage High Tri-State Leakage Current Tri-State Output Capacitance VOL VOH ILEAK COUT 5 ISINK = 200A ISOURCE = 200A 0.8 x OVDD 5 0.2 x OVDD V V A pF VHYST DIIN DCIN CLK at GND or VDD PD0 and PD1 at OGND or OVDD 5 0.1 5 5 0.7 x VDD 0.7 x OVDD 0.3 x VDD 0.3 x OVDD V A pF VCOM VREF RREFP RREFN VREFP - VREFN Measured between REFP and COM Measured between REFN and COM VREFP - VCOM VREFN - VCOM SYMBOL ISINK CONDITIONS MIN TYP 2 >500 -0.7 0.256 -0.256 VDD / 2 0.512 4 4 MAX UNITS mA k A V V V V k k
UNBUFFERED EXTERNAL REFERENCE (REFIN = GND, VREFP, VREFN, and VCOM are applied externally)
V
V
4
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Ultra-Low-Power, 22Msps, Dual 8-Bit ADC
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL 10pF at digital outputs, fCLK = 22MHz, CREFP = CREFN = CCOM = 0.33F, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER POWER REQUIREMENTS Analog Supply Voltage Digital Output Supply Voltage VDD OVDD Normal operating mode, fIN = 1.875MHz at -0.5dB FS, fCLK = 7.5MHz, CLK input from GND to VDD Normal operating mode, fIN = 5.5MHz at -0.5dB FS, fCLK = 22MHz, CLK input from GND to VDD Idle mode (tri-state), fIN = 1.875MHz at 0.5dB FS, fCLK = 7.5MHz, CLK input from GND to VDD Analog Supply Current IDD Idle mode (tri-state), fIN = 5.5MHz at -0.5dB FS, fCLK = 22MHz, CLK input from GND to VDD Standby mode, fCLK = 7.5MHz, CLK input from GND to VDD Standby mode, fCLK = 22MHz, CLK input from GND to VDD Shutdown mode, CLK = GND or VDD, PD0 = PD1 = OGND Normal operating mode, fIN = 1.875MHz at -0.5dB FS, fCLK = 7.5MHz, CL 10pF Normal operating mode, fIN = 5.5MHz at -0.5dB FS, fCLK = 22MHz, CL 10pF Digital Output Supply Current (Note 3) IODD Idle mode (tri-state), DC input, CLK = GND or VDD, PD0 = OVDD, PD1 = OGND Standby mode, DC input, CLK = GND or VDD, PD0 = OGND, PD1 = OVDD Shutdown mode, CLK = GND or VDD, PD0 = PD1 = OGND 9.1 2.7 1.8 4.2 3.0 3.6 VDD 5.0 V V SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX1192
9.1
10.5
4.2
mA
4.2 7.1 0.6 5.0 A
1.0 mA 2.9
0.1
5.0 A
0.1 0.1 5.0
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5
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC MAX1192
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL 10pF at digital outputs, fCLK = 22MHz, CREFP = CREFN = CCOM = 0.33F, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER TIMING CHARACTERISTICS CLK Rise to CHA Output Data Valid CLK Fall to CHB Output Data Valid CLK Rise/Fall to A/B Rise/Fall Time PD1 Rise to Output Enable PD1 Fall to Output Disable CLK Duty Cycle CLK Duty Cycle Variation Wake-Up Time from Shutdown Mode Wake-Up Time from Standby Mode Digital Output Rise/Fall Time INTERCHANNEL CHARACTERISTICS Crosstalk Rejection Amplitude Matching Phase Matching fIN,X = 5.5MHz at -0.5dB FS, fIN,Y = 0.3MHz at -0.5dB FS (Note 6) fIN = 5.5MHz at -0.5dB FS (Note 7) fIN = 5.5MHz at -0.5dB FS (Note 7) -75 0.03 0.1 dB dB Degrees tWAKE, SD (Note 5) tWAKE, ST (Note 5) 20% to 80% tDOA tDOB tDA/B tEN tDIS 50% of CLK to 50% of data, Figure 5 (Note 4) 50% of CLK to 50% of data, Figure 5 (Note 4) 50% of CLK to 50% of A/B, Figure 5 (Note 4) PD0 = OVDD PD0 = OVDD 1 1 1 6 6 6 5 5 50 10 20 5.4 2 8.5 8.5 8.5 ns ns ns ns ns % % s s ns SYMBOL CONDITIONS MIN TYP MAX UNITS
Note 1: Specifications +25C guaranteed by production test, <+25C guaranteed by design and characterization. Note 2: SNR, SINAD, SFDR, HD3, and THD are based on a differential analog input voltage of -0.5dB FS referenced to the amplitude of the digital output. SNR and THD are calculated using HD2 through HD6. Note 3: The power consumption of the output driver is proportional to the load capacitance (CL). Note 4: Guaranteed by design and characterization. Not production tested. Note 5: SINAD settles to within 0.5dB of its typical value. Note 6: Crosstalk rejection is measured by applying a high-frequency test tone to one channel and a low-frequency tone to the second channel. FFTs are performed on each channel. The parameter is specified as the power ratio of the first and second channel FFT test tone bins. Note 7: Amplitude/phase matching is measured by applying the same signal to each channel, and comparing the magnitude and phase of the fundamental bin on the calculated FFT.
6
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Ultra-Low-Power, 22Msps, Dual 8-Bit ADC MAX1192
Typical Operating Characteristics
(VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL 10pF at digital outputs, differential input at -0.5dB FS, fCLK = 22.005678MHz at 50% duty cycle, TA = +25C, unless otherwise noted.)
FFT PLOT CHANNEL A (DIFFERENTIAL INPUTS, 8192-POINT DATA RECORD)
MAX1192 toc01
FFT PLOT CHANNEL B (DIFFERENTIAL INPUTS, 8192-POINT DATA RECORD)
MAX1192 toc02
FFT PLOT CHANNEL A (DIFFERENTIAL INPUTS, 8192-POINT DATA RECORD)
-10 -20 AMPLITUDE (dB) -30 -40 -50 HD3 -60 -70 -80 -90 fINB HD2 fCLK = 22.005678MHz fINA = 8.056034MHz fINB = 5.606183MHz AINA = AINB = -0.5dB FS
MAX1192 toc03
0 -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 0 2 4 6 8 10 HD3 fINB HD2 fCLK = 22.005678MHz fINA = 5.606183MHz fINB = 8.056034MHz AINA = AINB = -0.5dB FS
0 -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 HD3 fINA HD2 fCLK = 22.005678MHz fINA = 5.606183MHz fINB = 8.056034MHz AINA = AINB = -0.5dB FS
0
12
0
2
4
6
8
10
12
0
2
4
6
8
10
12
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
FFT PLOT CHANNEL B (DIFFERENTIAL INPUTS, 8192-POINT DATA RECORD)
MAX1192 toc04
TWO-TONE IMD PLOT (DIFFERENTIAL INPUTS, 8192-POINT DATA RECORD)
-10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 fIN1 fIN2 fCLK = 22.005678MHz fIN1 = 1.8MHz fIN2 = 2.3MHz AIN = -7dB FS
MAX1192 toc05
0 -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 0 2 4 6 HD3
fCLK = 22.005678MHz fINA = 8.056034MHz fINB = 5.606183MHz AINA = AINB = -0.5dB FS
0
fINA
HD2
8
10
12
0
2
4
6
8
10
12
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
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7
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC MAX1192
Typical Operating Characteristics (continued)
(VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL 10pF at digital outputs, differential input at -0.5dB FS, fCLK = 22.005678MHz at 50% duty cycle, TA = +25C, unless otherwise noted.)
FFT PLOT CHANNEL A (SINGLE-ENDED INPUTS, 8192-POINT DATA RECORD)
MAX1192 toc06
FFT PLOT CHANNEL B (SINGLE-ENDED INPUTS, 8192-POINT DATA RECORD)
-10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 HD3 fINA HD2 fCLK = 22.005678MHz fINA = 5.606183MHz fINB = 8.056034MHz AINA = AINB = -0.5dB FS
MAX1192 toc07
0 -10 -20 AMPLITUDE (dB) -30 -40 -50 HD3 -60 -70 -80 -90 0 2 4 6 8 10 fINB HD2 fCLK = 22.005678MHz fINA = 5.606183MHz fINB = 8.056034MHz AINA = AINB = -0.5dB FS
0
12
0
2
4
6
8
10
12
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
FFT PLOT CHANNEL A (SINGLE-ENDED INPUTS, 8192-POINT DATA RECORD)
MAX1192 toc08
FFT PLOT CHANNEL B (SINGLE-ENDED INPUTS, 8192-POINT DATA RECORD)
-10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 HD3 fINA HD2 fCLK = 22.005678MHz fINA = 8.056034MHz fINB = 5.606183MHz AINA = AINB = -0.5dB FS
MAX1192 toc09
0 -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 0 2 4 6 8 10 HD3 fINB HD2 fCLK = 22.005678MHz fINA = 8.056034MHz fINB = 5.606183MHz AINA = AINB = -0.5dB FS
0
12
0
2
4
6
8
10
12
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
8
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Ultra-Low-Power, 22Msps, Dual 8-Bit ADC
Typical Operating Characteristics (continued)
(VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL 10pF at digital outputs, differential input at -0.5dB FS, fCLK = 22.005678MHz at 50% duty cycle, TA = +25C, unless otherwise noted.)
MAX1192
SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT FREQUENCY
MAX1192 toc10
SIGNAL-TO-NOISE AND DISTORTION vs. ANALOG INPUT FREQUENCY
49.5 49.0
MAX1192 toc11
50.0 49.5 49.0 CHANNEL B 48.0 47.5 47.0 46.5 46.0 0 25 50 75 100 CHANNEL A
50.0
SINAD (dB)
SNR (dB)
48.5
48.5 48.0 47.5 CHANNEL A 47.0 46.5 46.0
CHANNEL B
125
0
25
50
75
100
125
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
TOTAL HARMONIC DISTORTION vs. ANALOG INPUT FREQUENCY
MAX1192 toc12
SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT FREQUENCY
80 75 SFDR (dBc) CHANNEL A
MAX1192 toc13
-45 -50 -55 THD (dBc) -60 -65 -70 -75 -80 -85 0 25 50 75 100 CHANNEL A CHANNEL B
85
70 65 CHANNEL B 60 55 50 45
125
0
25
50
75
100
125
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
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9
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC MAX1192
Typical Operating Characteristics (continued)
(VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL 10pF at digital outputs, differential input at -0.5dB FS, fCLK = 22.005678MHz at 50% duty cycle, TA = +25C, unless otherwise noted.)
SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT POWER
MAX1192 toc14
SIGNAL-TO-NOISE AND DISTORTION vs. ANALOG INPUT POWER
fIN = 5.512345MHz 50 40 SINAD (dB) 30 20 10 0
MAX1192 toc15
60 fIN = 5.512345MHz 50 40 SNR (dB) 30 20 10 0 -30 -25 -20 -15 -10 -5 0 ANALOG INPUT POWER (dB FS)
60
-30
-25
-20
-15
-10
-5
0
ANALOG INPUT POWER (dB FS)
TOTAL HARMONIC DISTORTION vs. ANALOG INPUT POWER
MAX1192 toc16
SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT POWER
fIN = 5.512345MHz 70
MAX1192 toc17
-30 fIN = 5.512345MHz -40
80
THD (dBc)
-50
SFDR (dBc) -25 -20 -15 -10 -5
60
-60
50
-70
40
-80 -30 0 ANALOG INPUT POWER (dB FS)
30 -30 -25 -20 -15 -10 -5 0 ANALOG INPUT POWER (dB FS)
10
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Ultra-Low-Power, 22Msps, Dual 8-Bit ADC
Typical Operating Characteristics (continued)
(VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL 10pF at digital outputs, differential input at -0.5dB FS, fCLK = 22.005678MHz at 50% duty cycle, TA = +25C, unless otherwise noted.)
MAX1192
SIGNAL-TO-NOISE RATIO vs. SAMPLING RATE
MAX1192 toc18
SIGNAL-TO-NOISE AND DISTORTION vs. SAMPLING RATE
fIN = 5.512345MHz 49
MAX1192 toc19
50 fIN = 5.512345MHz 49
50
SINAD (dB)
SNR (dB)
48
48
47
47
46
46
45 0 10 20 30 fCLK (MHz) 40 50 60
45 0 10 20 30 fCLK (MHz) 40 50 60
TOTAL HARMONIC DISTORTION vs. SAMPLING RATE
MAX1192 toc20
SPURIOUS-FREE DYNAMIC RANGE vs. SAMPLING RATE
fIN = 5.512345MHz 75 70 SFDR (dBc) 65 60 55 50
MAX1192 toc21
-50 fIN = 5.512345MHz -55 -60 THD (dBc) -65 -70 -75 -80 0 10 20 30 fCLK (MHz) 40 50
80
60
0
10
20
30 fCLK (MHz)
40
50
60
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11
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC MAX1192
Typical Operating Characteristics (continued)
(VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL 10pF at digital outputs, differential input at -0.5dB FS, fCLK = 22.005678MHz at 50% duty cycle, TA = +25C, unless otherwise noted.)
SIGNAL-TO-NOISE RATIO vs. CLOCK DUTY CYCLE
MAX1192 toc22
SIGNAL-TO-NOISE AND DISTORTION vs. CLOCK DUTY CYCLE
fIN = 5.512345MHz 49
MAX1192 toc23
50 fIN = 5.512345MHz 49
50
SINAD (dB)
SNR (dB)
48
48
47
47
46
46
45 40 45 50 55 60 CLOCK DUTY CYCLE (%)
45 40 45 50 55 60 CLOCK DUTY CYCLE (%)
TOTAL HARMONIC DISTORTION vs. CLOCK DUTY CYCLE
MAX1192 toc24
SPURIOUS-FREE DYNAMIC RANGE vs. CLOCK DUTY CYCLE
78 76 74 SFDR (dBc) 72 70 68 66 64 62 fIN = 5.512345MHz
MAX1192 toc25
-60 -62 -64 -66 THD (dBc) -68 -70 -72 -74 -76 -78 -80 40
fIN = 5.512345MHz
80
45
50
55
60
60 40 45 50 55 60 CLOCK DUTY CYCLE (%)
CLOCK DUTY CYCLE (%)
12
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Ultra-Low-Power, 22Msps, Dual 8-Bit ADC
Typical Operating Characteristics (continued)
(VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL 10pF at digital outputs, differential input at -0.5dB FS, fCLK = 22.005678MHz at 50% duty cycle, TA = +25C, unless otherwise noted.)
INTEGRAL NONLINEARITY
MAX1192 toc26
MAX1192
DIFFERENTIAL NONLINEARITY
0.4 0.3 0.2 DNL (LSB) 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5
MAX1192 toc27
0.5 0.4 0.3 0.2 INL (LSB) 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 32 64 96
0.5
128 160 192 224 256
0
32
64
96
128 160 192 224 256
DIGITAL OUTPUT CODE
DIGITAL OUTPUT CODE
OFFSET ERROR vs. TEMPERATURE
MAX1192 toc28
GAIN ERROR vs. TEMPERATURE
VREFIN = 1.024V 0.45 0.40 GAIN ERROR (% FS) 0.35 0.30 0.25 0.20 0.15 0.10 -40 -15 10 35 60 85 CHANNEL A CHANNEL B
MAX1192 toc29
-0.50 -0.51 -0.52 OFFSET ERROR (% FS) -0.53 -0.54 -0.55 -0.56 -0.57 -0.58 -0.59 -0.60 -40 -15 10 35 60 CHANNEL B VREFIN = 1.024V CHANNEL A
0.50
85
TEMPERATURE (C)
TEMPERATURE (C)
INPUT BANDWIDTH vs. ANALOG INPUT FREQUENCY
MAX1192 toc30
REFERENCE VOLTAGE vs. ANALOG SUPPLY VOLTAGE
VDD = VREFIN 0.5125 VREFP - VREFN (V) 0.5120 0.5115 0.5110 0.5105 0.5100
MAX1192 toc31
REFERENCE VOLTAGE vs. TEMPERATURE
VDD = VREFIN 0.5125 VREFP - VREFN (V) 0.5120 0.5115 0.5110 0.5105 0.5100
MAX1192 toc32
6 4 2 GAIN (dB) 0 -2 -4 -6 -8 -10 1 10 100 FULL-POWER BANDWIDTH -0.5dB FS SMALL-SIGNAL BANDWIDTH -20dB FS
0.5130
0.5130
1000
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 VDD (V)
-40
-15
10
35
60
85
ANALOG INPUT FREQUENCY (MHz)
TEMPERATURE (C)
______________________________________________________________________________________
13
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC MAX1192
Typical Operating Characteristics (continued)
(VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL 10pF at digital outputs, differential input at -0.5dB FS, fCLK = 22.005678MHz at 50% duty cycle, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. INPUT FREQUENCY
3.0 DIGITAL SUPPLY CURRENT (mA) 2.5 2.0 1.5 1.0 0.5 0 0 2 4 6 fIN (MHz) 8 10 12 ANALOG SUPPLY CURRENT DIGITAL SUPPLY CURRENT
MAX1192 toc33
SUPPLY CURRENT vs. SAMPLING RATE
fIN = 5.5112345MHz 9.6 9.4 9.2 9.0 8.8 8.6 ANALOG SUPPLY CURRENT (mA) 20 SUPPLY CURRENT (mA) A 15 B 10 C 5
MAX1192 toc34
9.8
25
0 0 10 20 30 fCLK (MHz) A: ANALOG SUPPLY CURRENT (IDD) - INTERNAL AND BUFFERED EXTERNAL REFERENCE MODES B: ANALOG SUPPLY CURRENT (IDD) - UNBUFFERED EXTERNAL REFERENCE MODE C: DIGITAL SUPPLY CURRENT (IODD) - ALL REFERENCE MODES 40 50 60
Pin Description
PIN 1 2 3, 5, 10 4 6 7 8, 9, 28 11 12 13 14 15 16 17 18 19 20 21 22 NAME INAINA+ GND CLK INB+ INBVDD OGND OVDD D7 D6 D5 D4 A/B D3 D2 D1 D0 PD1 FUNCTION Channel A Negative Analog Input. For single-ended operation, connect INA- to COM. Channel A Positive Analog Input. For single-ended operation, connect signal source to INA+. Analog Ground. Connect all GND pins together. Converter Clock Input Channel B Positive Analog Input. For single-ended operation, connect signal source to INB+. Channel B Negative Analog Input. For single-ended operation, connect INB- to COM. Converter Power Input. Connect to a 2.7V to 3.6V power supply. Bypass VDD to GND with a combination of a 2.2F capacitor in parallel with a 0.1F capacitor. Output Driver Ground Output Driver Power Input. Connect to a 1.8V to VDD power supply. Bypass OVDD to GND with a combination of a 2.2F capacitor in parallel with a 0.1F capacitor. Tri-State Digital Output. D7 is the most significant bit (MSB). Tri-State Digital Output Tri-State Digital Output Tri-State Digital Output Channel Data Indicator. This digital output indicates channel A data (A/B = 1) or channel B data (A/B = 0) is present on the output. Tri-State Digital Output Tri-State Digital Output Tri-State Digital Output Tri-State Digital Output. D0 is the least significant bit (LSB). Power-Down Digital Input 1. See Table 3.
14
______________________________________________________________________________________
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC MAX1192
Pin Description (continued)
PIN 23 24 25 26 27 -- NAME PD0 REFIN COM REFN REFP EP Power-Down Digital Input 0. See Table 3. Reference Input. Internally pulled up to VDD. Common-Mode Voltage I/O. Bypass COM to GND with a 0.33F capacitor. Negative Reference I/O. Conversion range is (VREFP - VREFN). Bypass REFN to GND with a 0.33F capacitor. Positive Reference I/O. Conversion range is (VREFP - VREFN). Bypass REFP to GND with a 0.33F capacitor. Exposed Paddle. Internally connected to pin 3. Externally connect EP to GND. FUNCTION
Detailed Description
+ T/H
-
x2
FLASH ADC
DAC
1.5 BITS INA+ T/H INASTAGE 1 STAGE 2 STAGE 7
DIGITAL ERROR CORRECTION
D0-D7
Figure 1. Pipeline Architecture--Stage Blocks
The MAX1192 uses a seven-stage, fully differential, pipelined architecture (Figure 1) that allows for highspeed conversion while minimizing power consumption. Samples taken at the inputs move progressively through the pipeline stages every half-clock cycle. Including the delay through the output latch, the total clock-cycle latency is 5 clock cycles for channel A and 5.5 clock cycles for channel B. At each stage, flash ADCs convert the held input voltages into a digital code. The following digital-to-analog converter (DAC) converts the digitized result back into an analog voltage, which is then subtracted from the original held input signal. The resulting error signal is then multiplied by two, and the product is passed along to the next pipeline stage where the process is repeated until the signal has been processed by all stages. Digital error correction compensates for ADC comparator offsets in each pipeline stage and ensures no missing codes. Figure 2 shows the MAX1192 functional diagram.
VDD GND
/
INA+ T/H INA-
/
DEC
COM REFN INB+ T/H INB-
MULTIPLEXER
/
DEC
Figure 2. MAX1192 Functional Diagram ______________________________________________________________________________________ 15
/
PIPELINE ADC B
/
REFIN REFP
REFERENCE SYSTEM AND BIAS CIRCUITS
/
PIPELINE ADC A
MAX1192
POWER CONTROL
PD0 PD1 OVDD D0-D7
OUTPUT DRIVERS
A/B OGND
TIMING
CLK
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC MAX1192
INTERNAL BIAS S2a C1a S4a INA+ C2a S4c S1
COM S5a S3a
OUT
INAS4b C2b C1b S3b S2b INTERNAL BIAS INTERNAL BIAS S2a C1a S4a INB+ C2a S4c S1 S5b COM
OUT
HOLD TRACK
HOLD TRACK
CLK INTERNAL NONOVERLAPPING CLOCK SIGNALS
COM S5a S3a
OUT
MAX1192
OUT
INBS4b C2b C1b S3b S2b INTERNAL BIAS S5b COM
Figure 3. Internal T/H Circuits
Input Track-and-Hold (T/H) Circuits
Figure 3 displays a simplified functional diagram of the input T/H circuits. In track mode, switches S1, S2a, S2b, S4a, S4b, S5a, and S5b are closed. The fully differential circuits sample the input signals onto the two capacitors (C2a and C2b) through switches S4a and S4b. S2a and S2b set the common mode for the ampli16
fier input, and open simultaneously with S1, sampling the input waveform. Switches S4a, S4b, S5a, and S5b are then opened before switches S3a and S3b connect capacitors C1a and C1b to the output of the amplifier and switch S4c is closed. The resulting differential voltages are held on capacitors C2a and C2b. The amplifiers charge capacitors C1a and C1b to the same
______________________________________________________________________________________
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC MAX1192
Table 1. Reference Modes
VREFIN >0.8 x VDD REFERENCE MODE Internal reference mode. VREF is internally generated to be 0.512V. Bypass REFP, REFN, and COM each with a 0.33F capacitor. Buffered external reference mode. An external 1.024V 10% reference voltage is applied to REFIN. VREF is internally generated to be VREFIN/2. Bypass REFP, REFN, and COM each with a 0.33F capacitor. Bypass REFIN to GND with a 0.1F capacitor. Unbuffered external reference mode. REFP, REFN, and COM are driven by external reference sources. VREF is the difference between the externally applied VREFP and VREFN. Bypass REFP, REFN, and COM each with a 0.33F capacitor.
1.024V 10%
<0.3V
values originally held on C2a and C2b. These values are then presented to the first stage quantizers and isolate the pipelines from the fast-changing inputs. The wide input bandwidth T/H amplifiers allow the MAX1192 to track and sample/hold analog inputs of high frequencies (>Nyquist). Both ADC inputs (INA+, INB+, INA-, and INB-) can be driven either differentially or single ended. Match the impedance of INA+ and INA-, as well as INB+ and INB-, and set the common-mode voltage to midsupply (VDD/2) for optimum performance.
62.5A
MAX1192
4k
REFP
1.75V
0A COM
Analog Inputs and Reference Configurations
The MAX1192 full-scale analog input range is VREF with a common-mode input range of VDD/2 0.2V. VREF is the difference between V REFP and V REFN . The MAX1192 provides three modes of reference operation. The voltage at REFIN (VREFIN) sets the reference operation mode (Table 1). In internal reference mode, connect REFIN to VDD or leave REFIN unconnected. VREF is internally generated to be 0.512V 3%. COM, REFP, and REFN are lowimpedance outputs with VCOM = VDD/2, VREFP = VDD/2 + VREF/2, and VREFN = VDD/2 - VREF/2. Bypass REFP, REFN, and COM each with a 0.33F capacitor. In buffered external reference mode, apply a 1.024V 10% at REFIN. In this mode, COM, REFP, and REFN are low-impedance outputs with VCOM = VDD/2, VREFP = V DD /2 + V REFIN /4, and V REFN = V DD /2 - V REFIN /4. Bypass REFP, REFN, and COM each with a 0.33F capacitor. Bypass REFIN to GND with a 0.1F capacitor. In unbuffered external reference mode, connect REFIN to GND. This deactivates the on-chip reference buffers for COM, REFP, and REFN. With their buffers shut down, these nodes become high-impedance inputs (Figure 4) and can be driven through separate, external reference sources. Drive VCOM to VDD/2 10%, drive
1.5V 4k 62.5A REFN
1.25V
Figure 4. Unbuffered External Reference Mode Impedance
VREFP to (VDD/2 +0.256V) 10%, and drive VREFN to (VDD/2 - 0.256V) 10%. Bypass REFP, REFN, and COM each with a 0.33F capacitor. For detailed circuit suggestions and how to drive this dual ADC in buffered/unbuffered external reference mode, see the Applications Information section.
Clock Input (CLK)
CLK accepts a CMOS-compatible signal level. Since the interstage conversion of the device depends on the repeatability of the rising and falling edges of the external clock, use a clock with low jitter and fast rise and fall times (<2ns). In particular, sampling occurs on the rising edge of the clock signal, requiring this edge to
______________________________________________________________________________________
17
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC MAX1192
5 CLOCK-CYCLE LATENCY (CHA), 5.5 CLOCK-CYCLE LATENCY (CHB)
CHA
CHB tCLK tCL CLK tCH
tDOB A/B tDA/B D0-D7 D0B D1A CHB CHA
tDOA CHB CHA CHB CHA CHB CHA CHB CHA CHB CHA CHB
D1B
D2A
D2B
D3A
D3B
D4A
D4B
D5A
D5B
D6A
D6B
Figure 5. System Timing Diagram
provide lowest possible jitter. Any significant aperture jitter would limit the SNR performance of the on-chip ADCs as follows: 1 SNR = 20 x log 2 x x f IN x t AJ where fIN represents the analog input frequency and tAJ is the time of the aperture jitter. Clock jitter is especially critical for undersampling applications. The clock input should always be considered as an analog input and routed away from any analog input or other digital signal lines. The MAX1192 clock input operates with a VDD/2 voltage threshold and accepts a 50% 10% duty cycle (see Typical Operating Characteristics).
1111 1111 1111 1110 1111 1101
1LSB =
2 x VREF 256 VREF
VREF = VREFP - VREFN VREF
OFFSET BINARY OUTPUT CODE (LSB)
1000 0001 1000 0000 0111 1111
0000 0011 0000 0010 0000 0001 0000 0000
-128 -127 -126 -125 -1 0 +1
System Timing Requirements
Figure 5 shows the relationship between the clock, analog inputs, A/B indicator, and the resulting output data. Channel A (CHA) and channel B (CHB) are simultaneously sampled on the rising edge of the clock signal (CLK) and the resulting data is multiplexed at the output. CHA data is updated on the rising edge and CHB data is updated on the falling edge of the CLK. The A/B indicator follows CLK with a typical delay time of 6ns and remains high when CHA data is updated and low when CHB data is updated. Including the delay through the output latch, the total clock-cycle latency is 5 clock cycles for CHA and 5.5 clock cycles for CHB.
+125 +126 +127 +128
(COM) INPUT VOLTAGE (LSB)
Figure 6. Transfer Function
Digital Output Data (D0-D7), B Channel Data Indicator (A/B)
D0-D7 and A/B are TTL/CMOS-logic compatible. The digital output coding is offset binary (Table 2, Figure 6). The capacitive load on the digital outputs D0-D7 should be kept as low as possible (<15pF) to avoid large digital currents feeding back into the analog portion of the MAX1192 and degrading its dynamic performance. Buffers on the digital outputs isolate them from
18
______________________________________________________________________________________
VREF
VREF (COM)
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC MAX1192
Table 2. Output Codes vs. Input Voltage
DIFFERENTIAL INPUT VOLTAGE (IN+ - IN-) DIFFERENTIAL INPUT (LSB) +127 (+ full scale - 1 LSB) +126 (+ full scale - 2 LSB) +1 0 (bipolar zero) -1 -127 (- full scale + 1 LSB) - 128 (- full scale) OFFSET BINARY (D7-D0) 1111 1111 1111 1110 1000 0001 1000 0000 0111 1111 0000 0001 0000 0000 OUTPUT DECIMAL CODE 255 254 129 128 127 1 0
127 128 126 VREF x 128 1 VREF x 128 0 VREF x 128 1 -VREF x 128 127 -VREF x 128 VREF x -VREF x 128 128
Table 3. Power Logic
PD0 0 0 1 1 PD1 0 1 0 1 POWER MODE Shutdown Standby Idle Normal Operating ADC Off Off On On INTERNAL REFERENCE Off On On On CLOCK DISTRIBUTION Off On On On OUTPUTS Tri-state Tri-state Tri-state On
heavy capacitive loads. To improve the dynamic performance of the MAX1192, add 100 resistors in series with the digital outputs close to the MAX1192. Refer to the MAX1193 Evaluation Kit schematic for an example of the digital outputs driving a digital buffer through 100 series resistors.
Power Modes (PD0, PD1)
The MAX1192 has four power modes that are controlled with PD0 and PD1. Four power modes allow the MAX1192 to efficiently use power by transitioning to a low-power state when conversions are not required (Table 3). Shutdown mode offers the most dramatic power savings by shutting down all the analog sections of the MAX1192 and placing the outputs in tri-state. The
wake-up time from shutdown mode is dominated by the time required to charge the capacitors at REFP, REFN, and COM. In internal reference mode and buffered external reference mode, the wake-up time is typically 20s. When operating in the unbuffered external reference mode, the wake-up time is dependent on the external reference drivers. When the outputs transition from tri-state to on, the last converted word is placed on the digital outputs. In standby mode, the reference and clock distribution circuits are powered up, but the pipeline ADCs are unpowered and the outputs are in tri-state. The wakeup time from standby mode is dominated by the 5.4s required to activate the pipeline ADCs. When the outputs transition from tri-state to on, the last converted word is placed on the digital outputs.
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19
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC MAX1192
R4 600
R5 600
R1 600 VCOM = 1V TO 1.5V VSIG = 85mVP-P
RISO 22 INACIN 5pF
MAX1192
R2 300 R6 600 R3 600 R8 600 R9 600 R7 600 COM AV = 6V/V VCOM = VDD/2
RISO 22 CIN 5pF INA+
R10 600
R11 600
OPERATIONAL AMPLIFIERS CHOOSE EITHER OF THE MAX4452/MAX4453/MAX4454 SINGLE/ DUAL/QUAD +3V, 200MHz OP AMPS FOR USE WITH THIS CIRCUIT. CONNECT THE POSITIVE SUPPLY RAIL (VCC) TO 3V. CONNECT THE NEGATIVE SUPPLY RAIL (VEE) TO GROUND. DECOUPLE VCC WITH A 0.1F CAPACITOR TO GROUND.
RESISTOR NETWORKS RESISTOR NETWORKS ENSURE PROPER THERMAL AND TOLERANCE MATCHING. FOR R1, R2, AND R3 USE A NETWORK SUCH AS VISHAY'S 3R MODEL NUMBER 300192. FOR R4-R11, USE A NETWORK SUCH AS VISHAY'S 4R MODEL NUMBER 300197.
Figure 7. DC-Coupled Differential Input Driver
In idle mode, the pipeline ADCs, reference, and clock distribution circuits are powered, but the outputs are forced to tri-state. The wake-up time from idle mode is dominated by the 5ns required for the output drivers to start from tri-state. When the outputs transition from tristate to on, the last converted word is placed on the digital outputs. In the normal operating mode, all sections of the MAX1192 are powered.
Applications Information
The circuit of Figure 7 operates from a single 3V supply and accommodates a wide 0.5V to 1.5V input commonmode voltage range for the analog interface between an RF quadrature demodulator (differential, DC-coupled signal source) and a high-speed ADC. Furthermore, the circuit provides required SINAD and SFDR to demodulate a wideband (BW = 3.84MHz), QAM-16 communication link. RISO isolates the op amp output from the ADC capacitive input to prevent ringing and oscillation. CIN filters high-frequency noise.
20
______________________________________________________________________________________
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC MAX1192
25 INA+ 22pF 0.1F VIN N.C. 1 2 3 T1 6 VIN
REFP
1k 0.1F
RISO 50 INA+ CIN 22pF
MAX4108
5 4 2.2F 0.1F REFN 100 COM 1k
COM 0.1F RISO 50
MINICIRCUITS TT1-6-KK81 25 INA22pF 100
INACIN 22pF REFP
MAX1192
25 INB+ 22pF 0.1F VIN N.C. 1 2 3 T1 6 VIN 0.1F 1k RISO 50 INB+ 100 2.2F 0.1F REFN 25 INB22pF 100 0.1F RISO 50 INBCIN 22pF 1k CIN 22pF
MAX1192
MAX4108
5 4
MINICIRCUITS TT1-6-KK81
Figure 8. Transformer-Coupled Input Drive
Figure 9. Using an Op Amp for Single-Ended, AC-Coupled Input Drive
Using Transformer Coupling
An RF transformer (Figure 8) provides an excellent solution to convert a single-ended source signal to a fully differential signal, required by the MAX1192 for optimum performance. Connecting the center tap of the transformer to COM provides a VDD/2 DC level shift to the input. Although a 1:1 transformer is shown, a stepup transformer can be selected to reduce the drive requirements. A reduced signal swing from the input driver, such as an op amp, can also improve the overall distortion. In general, the MAX1192 provides better SFDR and THD with fully differential input signals than singleended drive, especially for high input frequencies. In differential input mode, even-order harmonics are lower as both inputs (INA+, INA- and/or INB+, INB-) are bal-
anced, and each of the ADC inputs only requires half the signal swing compared to single-ended mode.
Single-Ended AC-Coupled Input Signal
Figure 9 shows an AC-coupled, single-ended application. Amplifiers such as the MAX4108 provide high speed, high bandwidth, low noise, and low distortion to maintain the input signal integrity.
Buffered External Reference Drives Multiple ADCs
The buffered external reference mode allows for more control over the MAX1192 reference voltage and allows multiple converters to use a common reference. To drive one MAX1192 in buffered external reference mode, the external circuit must sink 0.7A, allowing one reference circuit to easily drive the REFIN of multiple converters to 1.024V 10%.
21
______________________________________________________________________________________
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC MAX1192
3V VDD REFIN
24 0.1F 1.248V 1 2 27 MAX6061 10Hz LOWPASS FILTER 1% 20k 0.33F 0.1F
REFP
N=1 MAX1192
3
26 0.33F
REFN
1F
1% 90.9k 3V 3 5 MAX4250 2 0.1F 0.1F 1 4 15 0.33F
25
COM GND
NOTE: ONE FRONT-END REFERENCE CIRCUIT PROVIDES 15mA OF OUTPUT DRIVE AND SUPPORTS OVER 1000 MAX1192s.
1.023V 24 VDD REFIN 0.1F 2.2F
27 0.33F
REFP N = 1000
MAX1192
26 0.33F 25 0.33F REFN
COM GND
Figure 10. External Buffered (MAX4250) Reference Drive Using a MAX6062 Bandgap Reference
Figure 10 shows the MAX6061 precision bandgap reference used as a common reference for multiple converters. The 1.248V output of the MAX6061 is divided down to 1.023V as it passes through a one-pole, 10Hz, lowpass filter to the MAX4250. The MAX4250 buffers the 1.023V reference before its output is applied to the MAX1192. The MAX4250 provides a low offset voltage (for high gain accuracy) and a low noise level.
Unbuffered External Reference Drives Multiple ADCs
The unbuffered external reference mode allows for precise control over the MAX1192 reference and allows multiple converters to use a common reference. Connecting REFIN to GND disables the internal reference, allowing REFP, REFN, and COM to be driven directly by a set of external reference sources.
22
______________________________________________________________________________________
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC MAX1192
3V
2.500V 0.1F 1 2 27 MAX6066 1% 30.1k 3 1/4 2 1F NOTE: ONE FRONT-END REFERENCE CIRCUIT SUPPORTS UP TO 160 MAX1192s 1% 10.0k 5 1/4 6 3V UNCOMMITTED 1M 12 1/4 1M 13 MAX4254 11 1% 49.9k 0.33F 0.1F 4 14 9 1% 10.0k 10 1/4 MAX4254 10F 6V 8 47 330F 6V 1.47k MAX4254 10F 6V 7 47 330F 6V 1.47k 1.248V 0.33F 26 0.33F 25 COM GND REFN 27 VDD REFP MAX4254 10F 6V 1 47 0.33F 330F 6V 1.47k 1.498V 0.33F 25 COM GND 0.33F 1.748V 26 REFN REFP VDD
N=1 MAX1192
REFIN 24
3
0.1F
2.2F
N = 160 MAX1192
REFIN 24
Figure 11. External Unbuffered Reference Driving 160 ADCs with MAX4254 and MAX6066
Figure 11 shows the MAX6066 precision bandgap reference used as a common reference for multiple converters. The 2.500V output of the MAX6066 is followed by a 10Hz lowpass filter and precision voltage-divider. The MAX4254 buffers the taps of this divider to provide the 1.75V, 1.5V, and 1.25V sources to drive REFP, REFN, and COM. The MAX4254 provides a low offset voltage and low noise level. The individual voltage followers are connected to 10Hz lowpass filters, which filter both the reference-voltage and amplifier noise to a level of 3nV/Hz. The 1.75V and 1.25V reference volt-
ages set the differential full-scale range of the associated ADCs at 0.5V. The common power supply for all active components removes any concern regarding power-supply sequencing when powering up or down. With the outputs of the MAX4252 matching better than 0.1%, the buffers and subsequent lowpass filters support as many as 160 MAX1192s.
______________________________________________________________________________________
23
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC MAX1192
A/B
MAX2451
INA+ INA0 90
MAX1192
INB+ INB-
DSP POSTPROCESSING
DOWNCONVERTER /8
Figure 12. Typical QAM Receiver Application
Typical QAM Demodulation Application
Quadrature amplitude modulation (QAM) is frequently used in digital communications. Typically found in spread-spectrum-based systems, a QAM signal represents a carrier frequency modulated in both amplitude and phase. At the transmitter, modulating the baseband signal with quadrature outputs, a local oscillator followed by subsequent upconversion can generate the QAM signal. The result is an in-phase (I) and a quadrature (Q) carrier component, where the Q component is 90 phase shifted with respect to the in-phase component. At the receiver, the QAM signal is demodulated into analog I and Q components. Figure 12 displays the demodulation process performed in the analog domain using the MAX1192 dual-matched, 3V, 8-bit ADC and the MAX2451 quadrature demodulator to recover and digitize the I and Q baseband signals. Before being digitized by the MAX1192, the mixed-down signal components can be filtered by matched analog filters, such as Nyquist or pulse-shaping filters. The filters remove unwanted images from the mixing process, thereby enhancing the overall signal-to-noise (SNR) performance and minimizing intersymbol interference.
ably on the same side as the ADC, using surfacemount devices for minimum inductance. Bypass VDD to GND with a 0.1F ceramic capacitor in parallel with a 2.2F bipolar capacitor. Bypass OVDD to OGND with a 0.1F ceramic capacitor in parallel with a 2.2F bipolar capacitor. Bypass REFP, REFN, and COM each to GND with a 0.33F ceramic capacitor. Multilayer boards with separated ground and power planes produce the highest level of signal integrity. Use a split ground plane arranged to match the physical location of the analog ground (GND) and the digital output driver ground (OGND) on the ADC's package. Connect the MAX1192 exposed backside paddle to GND. Join the two ground planes at a single point such that the noisy digital ground currents do not interfere with the analog ground plane. The ideal location of this connection can be determined experimentally at a point along the gap between the two ground planes, which produces optimum results. Make this connection with a low-value, surface-mount resistor (1 to 5), a ferrite bead, or a direct short. Alternatively, all ground pins could share the same ground plane, if the ground plane is sufficiently isolated from any noisy, digital systems ground plane (e.g., downstream output buffer or DSP ground plane). Route high-speed digital signal traces away from the sensitive analog traces of either channel. Make sure to isolate the analog input lines to each respective converter to minimize channel-to-channel crosstalk. Keep all signal lines short and free of 90 turns.
Grounding, Bypassing, and Board Layout
The MAX1192 requires high-speed board layout design techniques. Refer to the MAX1193 Evaluation Kit data sheet for a board layout reference. Locate all bypass capacitors as close to the device as possible, prefer-
24
______________________________________________________________________________________
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC
Dynamic Parameter Definitions
CLK
MAX1192
Aperture Jitter
Figure 13 depicts the aperture jitter (tAJ), which is the sample-to-sample variation in the aperture delay.
ANALOG INPUT tAD tAJ SAMPLED DATA (T/H)
Aperture Delay
Aperture delay (tAD) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken (Figure 13).
Signal-to-Noise Ratio (SNR)
TRACK HOLD TRACK
T/H
Figure 13. T/H Aperture Timing
Static Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. The static linearity parameters for the MAX1192 are measured using the end-point method.
For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC's resolution (N bits): SNRdB[max] = 6.02 x N + 1.76 In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental, the first five harmonics, and the DC offset.
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the the fundamental and the DC offset.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an actual step width and the ideal value of 1LSB. A DNL error specification of less than 1LSB guarantees no missing codes and a monotonic transfer function.
Effective Number of Bits (ENOB)
ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An ideal ADC's error consists of quantization noise only. ENOB for a full-scale sinusoidal input waveform is computed from: ENOB = SINAD - 1.76 6.02
Offset Error
Ideally, the midscale MAX1192 transition occurs at 0.5 LSB above midscale. The offset error is the amount of deviation between the measured transition point and the ideal transition point.
Gain Error
Ideally, the full-scale MAX1192 transition occurs at 1.5 LSB below full-scale. The gain error is the amount of deviation between the measured transition point and the ideal transition point with the offset error removed.
______________________________________________________________________________________
25
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC MAX1192
Total Harmonic Distortion (THD)
THD is typically the ratio of the RMS sum of the first five harmonics of the input signal to the fundamental itself. This is expressed as: V22 + V32 + V4 2 + V52 + V62 THD = 20 x log V1
Third-Order Intermodulation (IM3)
IM3 is the power of the worst third-order intermodulation product relative to the input power of either input tone when two tones, f1 and f2, are present at the inputs. The third-order intermodulation products are (2 x f1 f2), (2 x f2 f1). The individual input tone levels are at -7dB FS.
Power-Supply Rejection
Power-supply rejection is defined as the shift in offset and gain error when the power supplies are moved 5%.
where V1 is the fundamental amplitude, and V2-V6 are the amplitudes of the 2nd- through 6th-order harmonics.
Small-Signal Bandwidth
A small -20dB FS analog input signal is applied to an ADC in such a way that the signal's slew rate will not limit the ADC's performance. The input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased by -3dB. Note that the track/hold (T/H) performance is usually the limiting factor for the small-signal input bandwidth.
Third Harmonic Distortion (HD3)
HD3 is defined as the ratio of the RMS value of the third harmonic component to the fundamental input signal.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious component, excluding DC offset.
Full-Power Bandwidth
A large -0.5dB FS analog input signal is applied to an ADC, and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by -3dB. This point is defined as fullpower input bandwidth frequency.
Intermodulation Distortion (IMD)
IMD is the total power of the intermodulation products relative to the total input power when two tones, f1 and f2, are present at the inputs. The intermodulation products are (f1 f2), (2 x f1), (2 x f2), (2 x f1 f2), (2 x f2 f1). The individual input tone levels are at -7dB FS.
Chip Information
TRANSISTOR COUNT: 7925 PROCESS: CMOS
26
______________________________________________________________________________________
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) QFN THIN.EPS
L
REV.
MAX1192
0.15 C A
D2
C L
D
b D2/2
0.10 M C A B
PIN # 1 I.D.
D/2
0.15 C B
k
PIN # 1 I.D. 0.35x45
E/2 E2/2 E (NE-1) X e
C L
E2
k L
DETAIL A
e (ND-1) X e
C L
C L
L
e 0.10 C A 0.08 C
e
C
A1 A3
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE 16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm
APPROVAL DOCUMENT CONTROL NO.
21-0140
C
1 2
______________________________________________________________________________________
27
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC MAX1192
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
COMMON DIMENSIONS
EXPOSED PAD VARIATIONS
NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220. 10. WARPAGE SHALL NOT EXCEED 0.10 mm.
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE 16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm
APPROVAL DOCUMENT CONTROL NO. REV.
21-0140
C
2 2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
28 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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